Lab Goal: For this lab, you will code a System Verilog module to implement an up-down counter as described inthis document. This lab will require you to use two Seven-Segment Displays on the DE0-CV FPGA board. For thecounter, make use of the dff.sv modules or/and the modulo counter.Bonus: first five groups get 5 points bonus.Design Specifications: In this lab, you will design a mod 100 counter that outputs in base 10 (decimal) on twohex displays (HEX0 for one’s place and HEX1 for tens place; you will use your 7-segment decoder from Lab 1Milestone 2). Using the key buttons KEY0 and KEY1, you will either count up or down; as long as KEY0 is pressedyour numbers should count up, and as long as KEY1 is pressed your numbers should count down (if both orneither button is pressed, no increment/decrement should occur). For example, if you are counting up, thenumbers (on the hex displays) should go 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 10, 11, 12, 13, 14, 15, 16, …. 97,98, 99, 00, 01, 02, 03 and so on (vice-versa if you are counting down).The rate of increase/decrease of your numbers is decided by a switch input SW0. The rate of increase/decreaseof your numbers should be once per second if SW0 is off, and once per every 2 seconds if SW0 is on. Thecounter clock will be set up by making use of the native clock input on the board (PIN_M9). This is a pin on theDE0-CV board that provides a 50MHz clock input. In other words, this pin goes high 50 million times in asecond. Everything in your design that requires a clock should be clocked by PIN_M9. If you are not usingDE0-CV, you need to find the corresponding clock signal pin on your board.You should also have a reset pin, driven by SW5. When the reset pin is pressed, the counter should be reset to0, and it cannot count.In your top module, the first line should look like this:module mod100count(input logic clk, input logic rst , input logic SW0, input logic KEY0, input logic KEY1, outputlogic [6:0] HEX0, output logic [6:0] HEX1);In order to make a counter that tracks every second (as an example), you will need to use a signal which is setto go high for 1 clock period (of PIN_M9) within each second. One way to do this is to use a mod 50 millioncounter module. Note that you should be able to switch between these counting modes (i.e change once persecond or once every 2 seconds) on the fly.
Lab1 Milestone 2:
module Hex01(
input[3:0] S,
output logic [6:0] Z);
always_comb begin
unique case (S)
4’h0 : Z = 7’B1000000;
4’h1 : Z = 7’B1111001;
4’h2 : Z = 7’B0100100;
4’h3 : Z = 7’B0110000;
4’h4 : Z = 7’B0011001;
4’h5 : Z = 7’B0010010;
4’h6 : Z = 7’B0000010;
4’h7 : Z = 7’B1111000;
4’h8 : Z = 7’B0000000;
4’h9 : Z = 7’B0010000;
4’ha : Z = 7’B0001000;
4’hb : Z = 7’B0000011;
4’hc : Z = 7’B1000110;
4’hd : Z = 7’B0100001;
4’he : Z = 7’B0000110;
4’hf : Z = 7’B0001110;
endcase
end
endmodule