{"id":4279,"date":"2023-02-22T15:28:32","date_gmt":"2023-02-22T15:28:32","guid":{"rendered":"https:\/\/www.goodacademic.com\/blog\/questions\/counter-that-counts-to-99\/"},"modified":"2023-02-22T15:28:32","modified_gmt":"2023-02-22T15:28:32","slug":"counter-that-counts-to-99","status":"publish","type":"questions","link":"https:\/\/www.goodacademic.com\/blog\/questions\/counter-that-counts-to-99\/","title":{"rendered":"Counter that counts to 99"},"content":{"rendered":"
Learning Goal: <\/b>I’m working on a programming question and need support to help me learn.<\/p>\n

Lab Goal: For this lab, you will code a System Verilog module to implement an up-down counter as described in<\/p>\n

this document. This lab will require you to use two Seven-Segment Displays on the DE0-CV FPGA board. For the<\/p>\n

counter, make use of the dff.sv modules or\/and the modulo counter.<\/p>\n

Bonus: first five groups get 5 points bonus.<\/p>\n

Design Specifications: In this lab, you will design a mod 100 counter that outputs in base 10 (decimal) on two<\/p>\n

hex displays (HEX0 for one\u00e2\u20ac\u2122s place and HEX1 for tens place; you will use your 7-segment decoder from Lab 1<\/p>\n

Milestone 2). Using the key buttons KEY0 and KEY1, you will either count up or down; as long as KEY0 is pressed<\/p>\n

your numbers should count up, and as long as KEY1 is pressed your numbers should count down (if both or<\/p>\n

neither button is pressed, no increment\/decrement should occur). For example, if you are counting up, the<\/p>\n

numbers (on the hex displays) should go 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 10, 11, 12, 13, 14, 15, 16, …. 97,<\/p>\n

98, 99, 00, 01, 02, 03 and so on (vice-versa if you are counting down).<\/p>\n

The rate of increase\/decrease of your numbers is decided by a switch input SW0. The rate of increase\/decrease<\/p>\n

of your numbers should be once per second if SW0 is off, and once per every 2 seconds if SW0 is on. The<\/p>\n

counter clock will be set up by making use of the native clock input on the board (PIN_M9). This is a pin on the<\/p>\n

DE0-CV board that provides a 50MHz clock input. In other words, this pin goes high 50 million times in a<\/p>\n

second. Everything in your design that requires a clock should be clocked by PIN_M9. If you are not using<\/p>\n

DE0-CV, you need to find the corresponding clock signal pin on your board.<\/p>\n

You should also have a reset pin, driven by SW5. When the reset pin is pressed, the counter should be reset to<\/p>\n

0, and it cannot count.<\/p>\n

In your top module, the first line should look like this:<\/p>\n

module mod100count(input logic clk, input logic rst , input logic SW0, input logic KEY0, input logic KEY1, output<\/p>\n

logic [6:0] HEX0, output logic [6:0] HEX1);<\/p>\n

In order to make a counter that tracks every second (as an example), you will need to use a signal which is set<\/p>\n

to go high for 1 clock period (of PIN_M9) within each second. One way to do this is to use a mod 50 million<\/p>\n

counter module. Note that you should be able to switch between these counting modes (i.e change once per<\/p>\n

second or once every 2 seconds) on the fly.<\/p>\n

This is Lab 1 Milestone 2<\/p>\n

module Hex01(<\/p>\n

input[3:0] S,<\/p>\n

output logic [6:0] Z);<\/p>\n

always_comb begin<\/p>\n

unique case (S)<\/p>\n

4’h0 : Z = 7’B1000000;<\/p>\n

4’h1 : Z = 7’B1111001;<\/p>\n

4’h2 : Z = 7’B0100100;<\/p>\n

4’h3 : Z = 7’B0110000;<\/p>\n

4’h4 : Z = 7’B0011001;<\/p>\n

4’h5 : Z = 7’B0010010;<\/p>\n

4’h6 : Z = 7’B0000010;<\/p>\n

4’h7 : Z = 7’B1111000;<\/p>\n

4’h8 : Z = 7’B0000000;<\/p>\n

4’h9 : Z = 7’B0010000;<\/p>\n

4’ha : Z = 7’B0001000;<\/p>\n

4’hb : Z = 7’B0000011;<\/p>\n

4’hc : Z = 7’B1000110;<\/p>\n

4’hd : Z = 7’B0100001;<\/p>\n

4’he : Z = 7’B0000110;<\/p>\n

4’hf : Z = 7’B0001110;<\/p>\n

endcase<\/p>\n

end<\/p>\n

endmodule<\/p>\n<\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

Learning Goal: I’m working on a programming question and need support to help me learn. Lab Goal: For this lab, you will code a System Verilog module to implement an up-down counter as described in this document. This lab will require you to use two Seven-Segment Displays on the DE0-CV FPGA board. For the counter, […]<\/p>\n","protected":false},"author":3,"featured_media":0,"comment_status":"open","ping_status":"closed","template":"","meta":[],"disciplines":[732],"paper_types":[],"tagged":[],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/www.goodacademic.com\/blog\/wp-json\/wp\/v2\/questions\/4279"}],"collection":[{"href":"https:\/\/www.goodacademic.com\/blog\/wp-json\/wp\/v2\/questions"}],"about":[{"href":"https:\/\/www.goodacademic.com\/blog\/wp-json\/wp\/v2\/types\/questions"}],"author":[{"embeddable":true,"href":"https:\/\/www.goodacademic.com\/blog\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/www.goodacademic.com\/blog\/wp-json\/wp\/v2\/comments?post=4279"}],"version-history":[{"count":0,"href":"https:\/\/www.goodacademic.com\/blog\/wp-json\/wp\/v2\/questions\/4279\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.goodacademic.com\/blog\/wp-json\/wp\/v2\/media?parent=4279"}],"wp:term":[{"taxonomy":"disciplines","embeddable":true,"href":"https:\/\/www.goodacademic.com\/blog\/wp-json\/wp\/v2\/disciplines?post=4279"},{"taxonomy":"paper_types","embeddable":true,"href":"https:\/\/www.goodacademic.com\/blog\/wp-json\/wp\/v2\/paper_types?post=4279"},{"taxonomy":"tagged","embeddable":true,"href":"https:\/\/www.goodacademic.com\/blog\/wp-json\/wp\/v2\/tagged?post=4279"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}